The present invention relates generally to dynamic random access memories (DRAMs), and, more particularly, to a DRAM that is capable to operate at low supply voltage.
There are two forces that are currently drive power supply voltage on an integrated circuit (IC) chip to ever lower. One of the forces is a desire for portability of electronic equipment that can be operated by batteries. Such equipments include hearing aids, implantable cardiac pacemakers, cell phones, and hand held multimedia terminals. When a power supply voltage drops, the power consumption will drop by a square amount of that voltage.
Another driving force is the ever shrinking process technologies. Smaller geometry and thinner gate oxide of semiconductor devices cannot tolerate traditional 5V or even 3.3V power supply voltage. For instance, in a 0.13 um technology node, the power supply voltage is as low as 1.2V. Some time, even the external power supply voltage is 2.5V, which will have to be converted to 1.2V for internal circuits to properly operate. This is certainly the case for a state of the art DRAM chip.
A simplest DRAM cell comprises a single transistor and a single capacitor. If charges are stored in the capacitor, the cell is said to store a logic ‘1’, depending on the convention used. Then if no charges are present, the cell is said to store a logic ‘0’. Since the charges in the capacitor dissipates over time, DRAM systems require additional refreshing circuitries to periodically refresh the charges stored in the capacitors. But a capacitor can store only a very limited amount of charges, to fast distinguish the difference between a logic ‘1’ and a logic ‘0’, two bit lines are typically used for each bit with the first in the bit line pair known as a bit line true (BLT) and the other being the bit line complement (BLC). A sense amplifier compares BLT and BLC and outputs either a high or a low voltage to represent a logic value stored in the bit.
In order to gain speed and reliability, a half-Vdd (i.e., Vdd/2, where Vdd stands for a positive supply voltage) sensing scheme is commonly used, in which the bit-lines are pre-charged to a voltage of Vdd/2 prior to reading. When a particular cell is selected, the charges stored on the memory cell capacitor will be shared with the corresponding bit-line thus causing the voltage on the corresponding bit-line to rise above or fall below Vdd/2. While the complementary bit-line has no charge sharing, and hence stays at Vdd/2. A voltage difference between the bit-line pair is then sensed and amplified for reading the cell. The same applied to those cells connecting to bit line complements through the pass transistors.
The aforementioned Vdd/2 sensing scheme works very well when Vdd is sufficiently high, such as 3.3V. But its sensing speed and noise margin suffer when Vdd becomes lower. When the Vdd drops to 1.2V, and threshold voltages of N-type metal-oxide-semiconductor (NMOS) and P-type metal-oxide-semiconductor (PMOS) are about 0.3V and −0.3V, respectively. With the Vdd/2 sensing scheme, the headroom for the NMOS and PMOS transistors in the sense amplifier becomes 1.2V/2−0.3V=0.3V, which is very small for any high speed operation. In practice, the DRAM chip is required to be able to operate at Vdd=0.7V. Then the headroom of the sense amplifier is 0.05V, which is too marginal for the DRAM chip to work properly.
As such, what is desired is a DRAM sensing scheme that allows the DRAM chips to operate at a very low power supply voltage.